At least two problems are addressed by the present invention, chip area and chip fabrication turn-around-time. With respect to chip area, improvements are limited by the ability of designers to physically connect some structures to other structures without substantially increasing the area of a chip. For example, with electrically erasable programmable read only memory (EEPROM), there is increasingly a mismatch between the dimensions of drive circuitry that requires a relatively high voltage and the memory arrays that operate at low voltage. With each technology advance the arrays can get smaller and smaller, but, because of the need for high voltage, the drivers and decoders remain larger. More specifically, as photolithographic improvements permit the pitch of array word lines to decrease, the ability to fit individual word line drivers and decoders within the array pitch is strained because of the continuing high voltage write requirements for the word lines. Thus, the word line drivers and decoders can limit an array pitch that can otherwise be reduced, substantially increasing word line pitch above minimum dimensions and increasing the size of a chip needed for a given amount of memory.
Thus, a need exists for a way to accommodate the differing area requirements of interconnected structures within a semiconductor chip without sacrificing the ability to implement density improvements.
With respect to turn-around-time (the time it takes to design and manufacture a chip), fabrication speed has become vital to achieving a rapid time to market for new logic products. However, commonly accepted penalties for the achievement of a rapid turn-around time for programmable arrays, interconnects, or combinations of programmable arrays and bus interconnects, include lower circuit density, slower performance, interconnection inefficiency, and performance delays. Such is the case with programmable logic arrays (PLAs). Countering this, there is constant pressure to increase the density of semiconductor chips in general, and in particular PLAs.
Thus, a need exists for a way to decrease the turn-around time for PLAs while retaining high density for the array.